The invention relates to a logic circuit in which an output word can be formed from first and second input words using bit comparators and bit multiplexers.
A digital logic circuit of this type is disclosed in the publication entitled "A VLSI Fuzzy Logic Controller With Reconfigurable, Cascadable Architecture" by H. Watanabe et al from IEEE Journal of Solid-State Circuits, Volume 25, No. 2, April 1990 (pages 376 to 382). This concerns relatively detailed information on the design of a fuzzy logic controller, information being contained, inter alia, on circuitry for implementing fuzzy logic operators (minimum and maximum). The digital logic circuits (minimum and maximum functions) are relatively simply designed and have a multi-stage serial structure which, starting with the LSBs (least significant bits) of the input words and ending with the MSBs (most significant bits) of the input words do not enable valid bits of an output word until the MSB of the output word is present.
The Proceedings of the Twentieth International Symposium on Multiple-valued Logic, 23.-25. May 1990, Charlotte, N.C., USA, pages 122 to 125 discloses a maximum circuit of a quick fuzzy logic processing unit which comprises cascaded blocks having bit comparators and bit multiplexers, it being possible, starting with the MSB of the input words to carry a less-than carry signal and an equal-to carry signal from stage to stage as far as the LSB.
EDN Electrical Design News, Volume 34, No. 13, 22 June 1989, pages 232 to 234, VANDIVER: "Register performs binary search" discloses a comparator which comprises comparator blocks which are connected via lines for a less-than carry signal, an equal-to carry signal and a greater-than carry signal, the inputs for the carry signals for the block which contains the LSB being permanently prescribed, and it being possible for the carry signals to be carried from stage to stage as far as the block with the MSB.